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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
740
Total Papers
583
No Code
10
Twilight
147
Has Code
19.9%
Survival Rate
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EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data Transfer
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RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
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Dynamic Simultaneous Multithreaded Architecture
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CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories
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FPGA Technology Mapping Using Sketch-Guided Program Synthesis
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Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models
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PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
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Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study
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Efficient deadlock avoidance for 2D mesh NoCs that use OQ or VOQ routers
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NPS: A Framework for Accurate Program Sampling Using Graph Neural Network
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Customizing Trusted AI Accelerators for Efficient Privacy-Preserving Machine Learning
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Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption
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Low Latency CMOS Hardware Acceleration for Fully Connected Layers in Deep Neural Networks
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TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training
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VLSI Computational Architectures for the Arithmetic Cosine Transform
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PIMphony: Overcoming Bandwidth and Capacity Inefficiency in PIM-based Long-Context LLM Inference System
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Wireless BMS Architecture for Secure Readout in Vehicle and Second life Applications
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Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation
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Evolutionary Design of the Memory Subsystem
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Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration
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Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time
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TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering
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