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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
732
Total Papers
583
No Code
10
Twilight
139
Has Code
19.0%
Survival Rate
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A 588 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing
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Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
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FPGA Based Implementation of Deep Neural Networks Using On-chip Memory Only
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Death by README
LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
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Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (Extended Abstract)
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Using LLMs to Facilitate Formal Verification of RTL
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Enabling Compute-Communication Overlap in Distributed Deep Learning Training Platforms
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Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
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HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
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Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores
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Chain-NN: An Energy-Efficient 1D Chain Architecture for Accelerating Deep Convolutional Neural Networks
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PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes
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PolyAdd: Polynomial Formal Verification of Adder Circuits
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Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
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Tensor Casting: Co-Designing Algorithm-Architecture for Personalized Recommendation Training
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HDLdebugger: Streamlining HDL debugging with Large Language Models
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Detecting silent data corruptions in the wild
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MEIC: Re-thinking RTL Debug Automation using LLMs
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SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
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Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System
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An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
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HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
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