Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing
May 10, 2018 ยท Declared Dead ยท ๐ IEEE Computer Society Annual Symposium on VLSI
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Authors
Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan, Yanzhi Wang
arXiv ID
1805.04142
Category
cs.NE: Neural & Evolutionary
Cross-listed
cs.ET
Citations
1
Venue
IEEE Computer Society Annual Symposium on VLSI
Last Checked
4 months ago
Abstract
Recently, Deep Convolutional Neural Network (DCNN) has achieved tremendous success in many machine learning applications. Nevertheless, the deep structure has brought significant increases in computation complexity. Largescale deep learning systems mainly operate in high-performance server clusters, thus restricting the application extensions to personal or mobile devices. Previous works on GPU and/or FPGA acceleration for DCNNs show increasing speedup, but ignore other constraints, such as area, power, and energy. Stochastic Computing (SC), as a unique data representation and processing technique, has the potential to enable the design of fully parallel and scalable hardware implementations of large-scale deep learning systems. This paper proposed an automatic design allocation algorithm driven by budget requirement considering overall accuracy performance. This systematic method enables the automatic design of a DCNN where all design parameters are jointly optimized. Experimental results demonstrate that proposed algorithm can achieve a joint optimization of all design parameters given the comprehensive budget of a DCNN.
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