Energy and Performance Analysis of STTRAM Caches for Mobile Applications

August 08, 2019 Β· Declared Dead Β· πŸ› International Symposium on Embedded Multicore/Many-core Systems-on-Chip

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Authors Kyle Kuan, Tosiron Adegbija arXiv ID 1908.04744 Category cs.DC: Distributed Computing Cross-listed cs.ET Citations 1 Venue International Symposium on Embedded Multicore/Many-core Systems-on-Chip Last Checked 4 months ago
Abstract
Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics---and hence, STTRAM cache design requirements---differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.
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