Speeding-up Logic Design and Refining Hardware EDA Flow by Exploring Chinese Character based Graphical Representation
April 15, 2020 Β· Declared Dead Β· π arXiv.org
"No code URL or promise found in abstract"
Evidence collected by the PWNC Scanner
Authors
Shuangbai Xue, Yuan Xue
arXiv ID
2004.10675
Category
cs.PL: Programming Languages
Cross-listed
cs.AR
Citations
0
Venue
arXiv.org
Last Checked
4 months ago
Abstract
Electrical design automation (EDA) techniques have deeply influenced the computer hardware design, especially in the field of very large scale Integration (VLSI) circuits. Particularly, the popularity of FPGA, ASIC and SOC applications have been dramatically increased due to the well developed EDA tool chains. Over decades, improving EDA tool in terms of functionality, efficiency, accuracy and intelligence is not only the academic research hot spot, but the industry attempting goal as well. In this paper, a novel perspective is taken to review current mainstream EDA working flow and design methods, aiming to shorten the EDA design periods and simplify the logic design overload significantly. Specifically, three major contributions are devoted. First, a Chinese character based representation system (CCRS), which is used for presenting logical abstract syntax tree, is proposed. Second, the register-transfer-level (RTL) level symbolic description technique for CCRS are introduced to replace traditional text-based programming methods. Finally, the refined EDA design flow based on CCRS is discussed. It is convincing that the graphic non-pure-english based EDA flow could lower the design cost and complexity. As a fundamental trial in this new field, it is confirmative that a lot of following works will make the related EDA development prosperous.
Community Contributions
Found the code? Know the venue? Think something is wrong? Let us know!
π Similar Papers
In the same crypt β Programming Languages
R.I.P.
π»
Ghosted
R.I.P.
π»
Ghosted
Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractions
R.I.P.
π»
Ghosted
Glow: Graph Lowering Compiler Techniques for Neural Networks
R.I.P.
π»
Ghosted
Learnable Programming: Blocks and Beyond
R.I.P.
π»
Ghosted
Scenic: A Language for Scenario Specification and Scene Generation
R.I.P.
π»
Ghosted
Vandal: A Scalable Security Analysis Framework for Smart Contracts
Died the same way β π» Ghosted
R.I.P.
π»
Ghosted
Federated Learning: Strategies for Improving Communication Efficiency
R.I.P.
π»
Ghosted
In-Datacenter Performance Analysis of a Tensor Processing Unit
R.I.P.
π»
Ghosted
Deep Convolutional Neural Networks for Computer-Aided Detection: CNN Architectures, Dataset Characteristics and Transfer Learning
R.I.P.
π»
Ghosted