Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems
September 30, 2022 Β· Declared Dead Β· π IEEE computer architecture letters
"No code URL or promise found in abstract"
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Authors
Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz
arXiv ID
2210.00058
Category
cs.CR: Cryptography & Security
Cross-listed
cs.AR
Citations
6
Venue
IEEE computer architecture letters
Last Checked
4 months ago
Abstract
As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify data in memory that was never touched and is not owned by the chiplet which contains the Trojan. Further, the Trojan need not even be physically between the victim and the memory controller to attack the victim's memory transactions. Here, we explore the fundamental attack vectors possible in chiplet-based systems and provide an example Trojan implementation capable of directly modifying victim data in memory. This work aims to highlight the need for developing mechanisms that can protect and secure the coherence scheme from these forms of attacks.
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