Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing Machines, and Communication Protocols with FPGAs based on Concurrent Communicating Sequential Processes and the ConPro Synthesis Framework

Virtualization is the abstraction of details. Algorithms and programming languages provide abstraction, too. Virtualization of hardware and embedded systems is becoming more and more important in heterogeneous environments and networks, e.g., distributed and material-integrated sensor networks. Communication and data processing with a broad range of hardware and low-level protocols can be unified and accessed uniquely by introducing virtualization layers implemented directly in hardware on chip. Hardware design is today still component-driven (like a circuit board), rather than transforming algorithms as an abstraction layer directly into hardware designs. Programs and protocols are algorithms, so do not handle them as devices like in traditional high-level synthesis design flows! Complex reactive systems with dominant and complex control paths play an increasing role in SoC-design. The major contribution to concurrency appears at the control path level. This article gives an in-depth introduction to SoC-design methodology using the Highest-Level Synthesis ConPro compiler framework and a process-oriented programming language that provides a programming model based on concurrently executing and communicating sequential processes (CCSP) with an extensive set of interprocess-communication primitives. Circuits are modelled and programmed on an algorithmic level, more convenient and natural than component-driven designs. Extended case studies of a smart communication protocol router and an advanced stack-based processor providing a programmatical virtualization layer are shown and evaluated. Both are used together as a smart node architecture deployed in high density sensor-actuator-networks, e.g., for material-integrated intelligent systems.