Simple Linear-Size Additive Emulators

October 27, 2023 Β· Declared Dead Β· πŸ› SIAM Symposium on Simplicity in Algorithms

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Authors Gary Hoppenworth arXiv ID 2310.17886 Category cs.DS: Data Structures & Algorithms Citations 1 Venue SIAM Symposium on Simplicity in Algorithms Last Checked 4 months ago
Abstract
Given an input graph $G = (V, E)$, an additive emulator $H = (V, E', w)$ is a sparse weighted graph that preserves all distances in $G$ with small additive error. A recent line of inquiry has sought to determine the best additive error achievable in the sparsest setting, when $H$ has a linear number of edges. In particular, the work of [Kogan and Parter, ICALP 2023], following [Pettie, ICALP 2007], constructed linear size emulators with $+O(n^{0.222})$ additive error. It is known that the worst-case additive error must be at least $+Ξ©(n^{2/29})$ due to [Lu, Vassilevska Williams, Wein, and Xu, SODA 2022]. We present a simple linear-size emulator construction that achieves additive error $+O(n^{0.191})$. Our approach extends the path-buying framework developed by [Baswana, Kavitha, Mehlhorn, and Pettie, SODA 2005] and [Vassilevska Williams and Bodwin, SODA 2016] to the setting of sparse additive emulators.
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