SDT: Cutting Datacenter Tax Through Simultaneous Data-Delivery Threads
March 07, 2025 Β· Declared Dead Β· π IEEE computer architecture letters
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Authors
Amin Mamandipoor, Huy Dinh Tran, Mohammad Alian
arXiv ID
2503.05942
Category
cs.AR: Hardware Architecture
Cross-listed
cs.NI
Citations
0
Venue
IEEE computer architecture letters
Last Checked
3 months ago
Abstract
Networking is considered a datacenter tax, and hyperscalers push hard to provide high-performance networking with minimal resource expenditure. To keep up with the ever-increasing network rates, many CPU cycles are spent on the networking tax. We make a key observation that network processing threads can be simultaneously executed on server CPUs with minimal interference with the application threads. However, utilizing simultaneous multithreading (SMT) to scale the number of network threads with the number of application threads suffers from (1) failing to provide strict tail latency requirements for latency-critical applications, and (2) reducing the number of available hardware threads for application processes, thus contributing to a high datacenter network tax. In this work, we design, implement, and evaluate a chip-multiprocessor (CMP) with specialized Simultaneous Data-delivery Threads (SDT) per physical core. The key insight is that with judicious partitioning at the architectural level, SDT can safely co-run with application processes with guaranteed performance isolation. Our evaluation results, using full-system simulation, show that a 20-core CMP enhanced with SDT reduces the area and power consumption of a baseline 40-core CMP by 47.5% and 66%, respectively, while reducing network throughput by less than 10%.
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