Efficient Optimization Accelerator Framework for Multistate Ising Problems

May 26, 2025 Β· Declared Dead Β· πŸ› arXiv.org

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Authors Chirag Garg, Sayeef Salahuddin arXiv ID 2505.20250 Category cs.AR: Hardware Architecture Cross-listed cs.DC, cs.ET, cs.LG, stat.CO Citations 1 Venue arXiv.org Last Checked 3 months ago
Abstract
Ising Machines are emerging hardware architectures that efficiently solve NP-Hard combinatorial optimization problems. Generally, combinatorial problems are transformed into quadratic unconstrained binary optimization (QUBO) form, but this transformation often complicates the solution landscape, degrading performance, especially for multi-state problems. To address this challenge, we model spin interactions as generalized boolean logic function to significantly reduce the exploration space. We demonstrate the effectiveness of our approach on graph coloring problem using probabilistic Ising solvers, achieving similar accuracy compared to state-of-the-art heuristics and machine learning algorithms. It also shows significant improvement over state-of-the-art QUBO-based Ising solvers, including probabilistic Ising and simulated bifurcation machines. We also design 1024-neuron all-to-all connected probabilistic Ising accelerator on FPGA with the proposed approach that shows ~10000x performance acceleration compared to GPU-based Tabucol heuristics and reducing physical neurons by 1.5-4x over baseline Ising frameworks. Thus, this work establishes superior efficiency, scalability and solution quality for multi-state optimization problems.
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