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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
732
Total Papers
583
No Code
10
Twilight
139
Has Code
19.0%
Survival Rate
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Cicero: Addressing Algorithmic and Architectural Bottlenecks in Neural Rendering by Radiance Warping and Memory Optimizations
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HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
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A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing
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PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption
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PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System
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PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System
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Evaluating LLMs for Hardware Design and Test
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Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
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Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms
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BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication
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DeepNVM++: Cross-Layer Modeling and Optimization Framework of Non-Volatile Memories for Deep Learning
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Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
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A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
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CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework
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Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
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Dagger: Towards Efficient RPCs in Cloud Microservices with Near-Memory Reconfigurable NICs
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MP-Rec: Hardware-Software Co-Design to Enable Multi-Path Recommendation
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MLPerf Power: Benchmarking the Energy Efficiency of Machine Learning Systems from Microwatts to Megawatts for Sustainable AI
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E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
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Modular Hardware Design with Timeline Types
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MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks
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A Comparative Study between HLS and HDL on SoC for Image Processing Applications
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