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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
732
Total Papers
583
No Code
10
Twilight
139
Has Code
19.0%
Survival Rate
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Trinity: A General Purpose FHE Accelerator
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CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation
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Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads
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Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference
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VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
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Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications
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Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads
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Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems
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Physics-inspired Ising Computing with Ring Oscillator Activated p-bits
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MAGE: A Multi-Agent Engine for Automated RTL Code Generation
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SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy
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Hardware Trojan Detection Using Controlled Circuit Aging
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The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface
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A Single-Channel Architecture for Algebraic Integer Based 8$\times$8 2-D DCT Computation
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Fast and reconfigurable packet classification engine in FPGA-based firewall
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KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA
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FPRaker: A Processing Element For Accelerating Neural Network Training
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Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture
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The nanoPU: Redesigning the CPU-Network Interface to Minimize RPC Tail Latency
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In-Storage Embedded Accelerator for Sparse Pattern Processing
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SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs
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RPU: The Ring Processing Unit
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