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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
743
Total Papers
583
No Code
10
Twilight
150
Has Code
20.2%
Survival Rate
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Automated flow for compressing convolution neural networks for efficient edge-computation with FPGA
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Configurable memory systems for embedded many-core processors
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SoftmAP: Software-Hardware Co-design for Integer-Only Softmax on Associative Processors
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Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
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Laser Fault Injection Attacks against Radiation Tolerant TMR Registers
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A Lightweight Architecture for Real-Time Neuronal-Spike Classification
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DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans
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Test Primitive:A Straightforward Method To Decouple March
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Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
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Hybrid Intelligent Testing in Simulation-Based Verification
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VoxelCache: Accelerating Online Mapping in Robotics and 3D Reconstruction Tasks
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VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
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Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks
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A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks
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Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons
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SpiDR: A Reconfigurable Digital Compute-in-Memory Spiking Neural Network Accelerator for Event-based Perception
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Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model
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A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators
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SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
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COMET: A Framework for Modeling Compound Operation Dataflows with Explicit Collectives
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ELK: Exploring the Efficiency of Inter-core Connected AI Chips with Deep Learning Compiler Techniques
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NMP-PaK: Near-Memory Processing Acceleration of Scalable De Novo Genome Assembly
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