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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
743
Total Papers
583
No Code
10
Twilight
150
Has Code
20.2%
Survival Rate
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Harmonia: A Multi-Agent Reinforcement Learning Approach to Data Placement and Migration in Hybrid Storage Systems
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xPUE: Extending Power Usage Effectiveness Metrics for Cloud Infrastructures
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Proteus: Enabling High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic
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Performance and Power: Systematic Evaluation of AI Workloads on Accelerators with CARAML
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The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms
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Workload-Aware Hardware Accelerator Mining for Distributed Deep Learning Training
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Optimizing Offload Performance in Heterogeneous MPSoCs
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Relaxed exception semantics for Arm-A (extended version)
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Register Aggregation for Hardware Decompilation
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Hardware Implementation of Projection-Aggregation Decoders for Reed-Muller Codes
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T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU Reorganization
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Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption
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GPU Performance Portability needs Autotuning
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A Low-Power Streaming Speech Enhancement Accelerator For Edge Devices
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GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks
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A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training
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HashMem: PIM-based Hashmap Accelerator
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Hypersparse Traffic Matrix Construction using GraphBLAS on a DPU
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Collaborative Acceleration for FFT on Commercial Processing-In-Memory Architectures
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Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing
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Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network
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RCP: A Low-overhead Reversible Coherence Protocol
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