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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
743
Total Papers
583
No Code
10
Twilight
150
Has Code
20.2%
Survival Rate
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SAPA: Self-Aware Polymorphic Architecture
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FPGA Implementation of a Novel Image Steganography for Hiding Images
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Profiling-Assisted Decoupled Access-Execute
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Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
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AppSign: Multi-level Approximate Computing for Real-Time Traffic Sign Recognition in Autonomous Vehicles
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Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting
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A System Level Performance Evaluation for Superconducting Digital Systems
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HF-NTT: Hazard-Free Dataflow Accelerator for Number Theoretic Transform
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Cross-Layer Optimization for Fault-Tolerant Deep Learning
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EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
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RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
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Infra-Red, In-Situ (IRIS) Inspection of Silicon
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LearningGroup: A Real-Time Sparse Training on FPGA via Learnable Weight Grouping for Multi-Agent Reinforcement Learning
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RISC-V Toolchain and Agile Development based Open-source Neuromorphic Processor
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FPGA Random Number Generator
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An FPGA framework for Interferometric Vision-Based Navigation (iVisNav)
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In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
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Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
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zkPHIRE: A Programmable Accelerator for ZKPs over HIgh-degRee, Expressive Gates
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The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
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FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
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RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN
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