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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
759
Total Papers
568
No Code
21
Twilight
170
Has Code
22.4%
Survival Rate
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FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
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Testing Resource Isolation for System-on-Chip Architectures
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RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
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SONIQ: System-Optimized Noise-Injected Ultra-Low-Precision Quantization with Full-Precision Parity
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Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication
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Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
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YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
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A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
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NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
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Zeno: A Scalable Capability-Based Secure Architecture
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Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs
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History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
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3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence
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The Cartographer
Descriptor-Based Object-Aware Memory Systems: A Comprehensive Review
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Cocoon: A System Architecture for Differentially Private Training with Correlated Noises
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A Near-Cache Architectural Framework for Cryptographic Computing
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OpenGL GPU-Based Rowhammer Attack (Work in Progress)
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A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryption
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SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
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Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
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Offloading Data Center Tax
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QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecture
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