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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
759
Total Papers
568
No Code
21
Twilight
170
Has Code
22.4%
Survival Rate
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Learning Cache Coherence Traffic for NoC Routing Design
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Anvil: A General-Purpose Timing-Safe Hardware Description Language
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Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations
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Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory
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ASDR: Exploiting Adaptive Sampling and Data Reuse for CIM-based Instant Neural Rendering
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Leveraging Highly Approximated Multipliers in DNN Inference
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A Runtime-Adaptive Transformer Neural Network Accelerator on FPGAs
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Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception
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Accelerating DNA Read Mapping with Digital Processing-in-Memory
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WWW: What, When, Where to Compute-in-Memory
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Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
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Power Aware Scheduling of Tasks on FPGAs in Data Centers
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Reducing the memory usage of Lattice-Boltzmann schemes with a DWT-based compression
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Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing Machines, and Communication Protocols with FPGAs based on Concurrent Communicating Sequential Processes and the ConPro Synthesis Framework
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Architectural Support for Efficient Data Movement in Disaggregated Systems
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Third ArchEdge Workshop: Exploring the Design Space of Efficient Deep Neural Networks
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An Embedded RISC-V Core with Fast Modular Multiplication
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Optimizing Graph Processing and Preprocessing with Hardware Assisted Propagation Blocking
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Compiler Directed Speculative Intermittent Computation
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A Retrospective Recount of Computer Architecture Research with a Data-Driven Study of Over Four Decades of ISCA Publications
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Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
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IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping
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