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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
759
Total Papers
568
No Code
21
Twilight
170
Has Code
22.4%
Survival Rate
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HOMI: Ultra-Fast EdgeAI platform for Event Cameras
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E2ATST: A Temporal-Spatial Optimized Energy-Efficient Architecture for Training Spiking Transformer
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ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors
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What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips
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Analysis of a Memcapacitor-Based for Neural Network Accelerator Framework
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Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training
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PENDRAM: Enabling High-Performance and Energy-Efficient Processing of Deep Neural Networks through a Generalized DRAM Data Mapping Policy
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HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators
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Dynamic neural network with memristive CIM and CAM for 2D and 3D vision
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Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver
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Improvements in Interlayer Pipelining of CNN Accelerators Using Genetic Algorithms
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C3S Micro-architectural Enhancement: Spike Encoder Block and Relaxing Gamma Clock (Asynchronous)
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Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators
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A Hardware Accelerator for the Goemans-Williamson Algorithm
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Fast and Efficient Merge of Sorted Input Lists in Hardware Using List Offset Merge Sorters
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A Tensor Compiler for Processing-In-Memory Architectures
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Optimizing Attention on GPUs by Exploiting GPU Architectural NUMA Effects
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F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs
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On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach
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Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis
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UPMEM Unleashed: Software Secrets for Speed
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Intent-Driven Storage Systems: From Low-Level Tuning to High-Level Understanding
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