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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
732
Total Papers
583
No Code
10
Twilight
139
Has Code
19.0%
Survival Rate
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DiVa: An Accelerator for Differentially Private Machine Learning
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Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
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GreenLLM: Disaggregating Large Language Model Serving on Heterogeneous GPUs for Lower Carbon Emissions
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LLM-Aided Compilation for Tensor Accelerators
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VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
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Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
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PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips
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Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
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Revising the classic computing paradigm and its technological implementations
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ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers
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Tearing Down the Memory Wall
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Flat ORAM: A Simplified Write-Only Oblivious RAM Construction for Secure Processors
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OpenSpike: An OpenRAM SNN Accelerator
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LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training
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Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge
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Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
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Characterizing the impact of last-level cache replacement policies on big-data workloads
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Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing
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LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
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Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework
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AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models
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A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
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