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🏛️ The Hardware Architecture Crypt
cs.AR: Where Hardware Architecture papers rest without their code.
759
Total Papers
568
No Code
21
Twilight
170
Has Code
22.4%
Survival Rate
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Enthuse: Efficient Adaptable High-throughput Streaming Aggregation Engines
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Anteumbler: Non-Invasive Antenna Orientation Error Measurement for WiFi APs
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Enabling New HDLs with Agents
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ChiBench: a Benchmark Suite for Testing Electronic Design Automation Tools
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There and Back Again: A Netlist's Tale with Much Egraphin'
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End-to-End Transformer Acceleration Through Processing-in-Memory Architectures
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Layer-wise Weight Selection for Power-Efficient Neural Network Acceleration
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Unsupervised Graph Neural Network Framework for Balanced Multipatterning in Advanced Electronic Design Automation Layouts
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QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable Attention
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Neo: Real-Time On-Device 3D Gaussian Splatting with Reuse-and-Update Sorting Acceleration
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TIMERIPPLE: Accelerating vDiTs by Understanding the Spatio-Temporal Correlations in Latent Space
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DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
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KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic Arrays
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VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation
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Understanding the Error Sensitivity of Privacy-Aware Computing
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AGS: Accelerating 3D Gaussian Splatting SLAM via CODEC-Assisted Frame Covisibility Detection
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Disaggregated Architectures and the Redesign of Data Center Ecosystems: Scheduling, Pooling, and Infrastructure Trade-offs
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RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs
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Synapse: Virtualizing Match Tables in Programmable Hardware
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Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs
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SDT: Cutting Datacenter Tax Through Simultaneous Data-Delivery Threads
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VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
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